The IC 24LC01/24LC02 uses the I2C addressing proto- col and 2-wire serial interface which includes a bidirec- tional serial data bus synchronized by a clock. Microchip 24LC02 EEPROM are available at Mouser Electronics. Mouser offers inventory, pricing, & datasheets for Microchip 24LC02 EEPROM. Description, Bit/Bit Serial EePROM Write Protect Memory Chips. Company, Pronics. Datasheet, Download 24LC02 datasheet. Quote. Find where to.
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Once the stop condition for a write command has been issued from the master, the device initiates the internally timed write cycle.
Clock and data transition. Partial page write allowed. Characteristics Functional Description Timing Diagrams.
Serial clock data input. After this period the first clock pulse is generated.
The SDA pin is bidirectional for serial data transfer. The pin is open-drain driven and may be wired-OR with any number of other open-drain or open collector devices. The microcontroller must terminate the page write sequence with a stop condition. Output Capacitance See Note. During data transfer, the data line must remain stable whenever the clock line is high.
Search field Part name Part description. Internally organized with 8-bit words, the 1K requires a 7-bit data word address for random word addressing. Internally organized with 8-bit words, the 2K requires an 8-bit data word address for random word addressing. Write operation with built-in timer. Input Capacitance See Note. Data Input Hold Time.
Daasheet Valid from Clock. Hardware controlled write protection. ACK polling can be initiated immediately. A write operation requires an 8-bit data word address following the device address word and acknowledgment.
A page write is initiated the same as byte write, but the microcontroller does not send a stop condition after the first data word is clocked in. The device is optimized for use in many industrial and com.
24LC02 PDF Datasheet浏览和下载
After receiving the 8-bit data word, the EEPROM will output a zero and the address- ing device, such as a microcontroller, must terminate the write sequence with a stop con- dition. Functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability. Since the device will not acknowledge during a write cycle, this can be used to determine when the cycle is complete this feature can be used to maximize bus throughput.
Time in which the bus must be free before a new transmission can start. Instead, after datasehet EEPROM ac- knowledges the receipt of the first dayasheet word, the microcontroller can transmit up to seven more data dztasheet.
The device address word consist of a mandatory one, zero sequence for the first four most significant bits refer to the diagram show- ing the Device Address.
These are stress ratings only. If the device is still busy with the. These three bits must compare to their corresponding hard-wired input pins.
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This happens during the ninth clock cycle. If not, the chip will return to a standby state. A read operation is initi- ated if this bit is high and a write operation is initiated if this bit is low.
For relative timing, refer to timing diagrams.
Stresses exceeding the range specified under “Absolute Maxi. Commerical temperature range 0.
The higher data word address bits are not incremented, re- taining the memory page row location refer to Page write timing. Data Input Setup Time. Data transfer may be initiated only when the. Upon receipt of this ad- dress, the EEPROM will again respond with a zero and then clock in the first 8-bit data word.